Apparatus and method for processing pipelined data

ABSTRACT

Apparatus ( 3 ) for processing pipelined data, comprises a storage unit and at least one logic unit ( 11 ) for executing operations on a block ( 4 ) of data. The storage means comprises an instruction table ( 12   a ) comprising at least one instruction, and the at least one logic unit ( 11 ) is in at least one pipelined processing stage adapted to receive the block ( 4 ) and a first instruction ( 13   a ) of the at least one instruction and execute the first instruction ( 13   a ). The invention also relates to a method for processing pipelined data, a module ( 1 ) for processing pipelined data, an integrated circuit ( 15 ), a circuit board assembly ( 16 ), a computer unit ( 22 ) and a pipelined processing system.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a method for processing pipelined data,a processing means for pipelined data, a module for processing pipelineddata, an integrated circuit, a circuit board assembly, a computer unitand a pipelined processing system.

DESCRIPTION OF RELATED ART

Many processors use a technique called pipelining or pipelinedprocessing, where the processors begin to execute a second instructionbefore a first instruction has been completed, That is, severalinstructions are in a “pipeline” simultaneously, each at a differentprocessing stage. The pipeline is divided into stages, i.e. segments,and each stage can execute its operations, i.e. defined actionsassociated with an instruction, concurrently with the other stages. Whena stage completes an operation, it passes the result to the next stagein the pipeline and obtains the next operation from the preceding stage.The final results of each instruction emerge at the end of the pipelinein rapid succession.

Not only high performance and RISC (Reduced Instruction Set Computer)based microprocessors use instruction pipelining. RISC gives a highprogrammability for the instructions performed by the microprocessor andhigher demands on the software than for CISC (Complex Instruction Setcomputer) based microprocessors. Although RISC-based microprocessorshave a faster clock frequency than CISC-based microprocessors, they areslower for certain special purposes, for which a CISC may be configured.However, generally for special purposes, both the RISC and the CISC areslower than ASIC (Application Specific Integrated Circuit), since theASIC is especially adapted for a specific purpose. Since the ASIC isoptimised for a specific, predetermined work, it has the disadvantage ofnot being adapted for other purposes and thereby lacking the flexibilityof the general-purpose microprocessors. U.S. Pat. No. 6,157,955-Adiscloses a general-purpose programmable packet-processing platform foraccelerating network infrastructure applications. Acceleration isachieved by e.g. dividing the steps of the packet processing into amultiplicity of pipeline stages and providing custom, specialisedclassification engines and a general-purpose microprocessor, called apolicy processor, for executing the arbitrary actions desired by certainapplications. However, the policy processor has to perform the desiredaction before an execution of a subsequent, requested action is able tobegin.

SUMMARY

It is a general object of the present invention to provide a computerarchitecture that for specific applications allows faster instructionexecution than generally RISC- and CISC-based microprocessors and thatis more flexible than an ASIC regarding programmability.

The present invention therefore provides a method for pipelinedprocessing. The method comprises at least one pipelined processingstage, which comprises the steps of:

receiving a block and a first program counter, i.e. a variable used tokeep track of the address of the next instruction, in a processingmeans, where the first program counter is associated with the block;

looking up, i.e. selecting within a predefined table of values (array,matrix, etc), a first instruction corresponding to the first programcounter in an instruction table comprising at least the firstinstruction; and

executing at least one operation associated with the first instructionin a logic unit. Hereby is achieved that every stage in the pipelinedprocessing of incoming blocks is associated with an instruction table,in which an instruction specified for an application is editable so asto custom-configure each stage for a specific application.

Suitably, the at least one pipelined processing stage comprises the stepof:

receiving at least one argument, i.e. a variable, in the processingmeans, where the at least one argument is associated with the block; and

the executing of the at least one operation in the logic unit isperformed on the at least one argument, the block or both the at leastone argument and the block.

Hereby is achieved that more complex and different instructions may beprogrammed in the instruction table.

Preferably, before the above mentioned stage or stages, the methodcomprises the steps of:

receiving a search vector associated with the block in a classificationmeans;

comparing the search vector with data stored in an associative storage,the data

comprising the first program counter and the at least one argument; and

sending the at least one argument and the first program counter to theprocessing means

before the at least one processing stage.

Hereby a classification stage before the, processing stage is achieved,wherein the at least one argument and the first program counter, whichmay be different for each type of block that is sent to theclassification means, determine a possible modification of the block inthe first stage in the processing means. The associative storage, i.e. astorage that is accessed by comparing the content of the data stored init rather than by addressing predetermined locations, is programmable,which makes the pipelining processing even more flexible compared toprocessing in an ASIC.

Advantageously, the method comprises the steps of:

creating a second program counter in a first stage, and

creating a third program counter in a second stage. Hereby is achievedthat conditional jumps are possible when a possible correspondingconditional jump instruction is executed in the first or the secondstage.

The invention also relates to a processing means for processingpipelined data. The processing means comprises a storage means and atleast one logic unit for executing operations on a block of data. Thestorage means comprises an instruction table comprising at least oneinstruction. The at least one logic unit is in at least one pipelinedprocessing stage adapted to receive the block and a first instruction ofthe at least one instruction and execute at least one operationassociated with the first instruction.

Suitably, the at least one logic unit in the at least one pipelinedprocessing stage is adapted to receive at least one argument associatedwith the block and execute the at least one operation on the block, theat least one argument or both the block and the at least one argument.

Preferably, the instruction table comprises at least a secondinstruction. Hereby the option of using conditional jumps in duringpipelined processing is achieved.

In a first aspect of the processing means according to the invention,the block is a PDU (Protocol Data unit), e.g. a part of an IP-packet.Hereby is achieved that the processing means may, for example, be usedin an apparatus in a communications network, such as the Internet.

In a second aspect of the processing means, the block comprises adigital representation of an analogue signal sequence. Hereby isachieved that the processing means may be used for digital signalprocessing.

Suitably, the logic unit comprises an ALU and means for picking out apart or parts of the block.

Furthermore, the invention relates to a module for processing pipelineddata. The module comprises a classification means for matching oridentifying a block of data and a processing means for processing theblock. The processing means comprises storage means and at least onelogic unit for executing operations on the block, which is deliveredfrom the classification means to the processing means. Theclassification means is adapted to send a program counter associatedwith the block to the processing means and the storage means comprisesan instruction table comprising at least one instruction. The at leastone logic unit is in at least one pipelined processing stage adapted toreceive the block and a first instruction of the at least oneinstruction and execute at least one operation associated with the firstinstruction.

Suitably, the classification means is adapted to send at least oneargument associated with the block to the processing means, and the atleast one logic unit in the at least one pipelined processing stage isadapted to receive the at least one argument and execute the at leastone operation on the block, the at least one argument, or both the blockand the at least one argument.

In addition, the invention also relates to an integrated circuit, whichcomprises at least one module according to the above.

Moreover, the invention relates to a circuit board assembly, e.g. a linecard adapted for a router. The circuit board assembly comprises at leastone integrated circuit comprising at least one module according to theabove.

Furthermore, the invention relates to a computer unit, such as networkcomputer unit or a signal processing computer unit, comprising at leastone integrated circuit, where the at least one integrated circuitcomprises at least one module according to the above.

Also, the invention relates to a pipelined processing system, comprisinga classification means for matching or identifying a block of data, astorage means and a processing means for processing the block. Theprocessing means comprises at least one logic unit for executingoperations on the block, which is delivered from the classificationmeans to the processing means. The classification means is adapted tosend a program counter associated with the block to the processing meansand the storage means comprises an instruction table comprising at leastone instruction. The at least one logic unit is in at least oneprocessing stage adapted to receive the block and a first instruction ofthe at least one instruction and execute at least one operationassociated with the first instruction.

BRIEF DESCRIPTION OF THE DRAWINGS

The objects, advantages and effects as well as features of the presentinvention will be more readily understood from the following detaileddescription of a preferred embodiment of the invention, as well as otherembodiments, when read together with the accompanying drawings, inwhich:

FIG. 1 schematically shows a module for pipelined processing of dataaccording to the invention;

FIG. 2 illustrates the function of a classification means according tothe invention;

FIG. 3 schematically shows an overview of the method of operation of aprocessing means according to the invention;

FIG. 4 shows in more detail two processing stages in the processingmeans according to FIG. 3;

FIG. 5 shows a schematic view of a circuit board assembly according toan embodiment of the invention;

FIG. 6 schematically shows a router according to the invention; and

FIG. 7 shows a schematic block diagram of components on a line cardaccording to the invention.

DETAILED DESCRIPTION OF EMBODIMENTS

While the invention covers various modifications and alternative methodsand systems, preferred embodiments of the invention are shown in thedrawings and will hereinafter be described in detail. It is to beunderstood, however, that the specific description and drawings are notintended to limit the invention to the specific forms disclosed. On thecontrary, it is intended that the scope of the claimed inventionincludes all modifications and alternative constructions thereof fallingwithin the spirit and scope of the invention as expressed in theappended claims to the full range of their equivalents.

A module 1, which comprises a classification means 2 and a processingmeans 3 for pipelined processing according to the invention, isschematically illustrated in FIG. 1. A block 4 in the form of a PDU,such as a part of an IP-packet (Internet Protocol packet), is receivedby the classification means 2. A search vector 5 associated andretrieved from the block 4 is also received by the classification means2. The block 4 is forwarded by the classification means 2 to theprocessing means 3 without changing the block 4. The processing means 3also receives at least one argument 6 and a first program counter 7 afrom the classification means 2. Thereafter, the processing means 3 mayperform different operations on the block 4, dependent on, for instance,the type of block that has been classified by the classification means.The processing means 3 sends out the changed or the unchanged block 4from the module 1. For performing a desired task, several modules can beserially coupled to each other, thus creating an architecture ofalternating classification means 2 and processing means 3. For thepurpose of serially coupled modules, a second search vector (not shown)is created by the processing means and may be sent to a possible second,serially coupled module (not shown).

The classification means 2 will now be described more in detail withreference to FIG. 2. Here the search vector 5 is compared to characterstrings in at least one column in an associative storage 8 (CAM=ContentAddressable Memory). An associative storage is known to a person skilledin the art and is therefore not described more in detail. After thecomparison, the first program counter 7 a and the argument/arguments 6corresponding to the search vector 5 are sent from the classificationmeans 2 to the processing means 3. The block 4 is forwarded through theclassification means 2 without being changed. The forwarding is delayedso as to send the block 4 to the processing means 3 substantially at thesame time as the argument/arguments 6 and the first program counter 7 a.Hereinafter, the description only refers to one argument 6, but it is tobe understood that several arguments for each block could be sent,stored and edited in the processing means.

FIG. 3 schematically shows the basic method of operation of theprocessing means 3. Here, the processing of the pipelined blocks of datacomprises five processing stages 9 a–9 e where each stage is processedin one clock cycle, but of course the pipelined processing in theprocessing means 3 may comprise down to only one stage or much more thanfive stages. The principles of pipelining are known to a person ordinaryskilled in the art, and therefore only the processing of one block andits associated argument and program counters are described. Before andafter each stage 9 a–9 e, input data and output data are stored in oneregister each, i.e. a small, high-speed computer circuit that holdsvalues of internal operations. The top flow of the three, separated,parallel flows shown in FIG. 3 through the processing means 3,illustrates the processing of the block 4. The middle flow illustratesthe processing of the associated argument 6 and the lowest flowillustrates the receiving of a program counter for every stage. As willbe explained in the following, the block may be changed in each stage,the argument may be changed in each stage, and a new program counter iscreated in every new stage.

FIG. 4 shows the first two stages, 9 a and 9 b, of the five stages shownin FIG. 3. It is to be understood that the other three stages 9 c–9 eoperate in the same principal way as the first two stages, 9 a and 9 b,and therefore have been left out. On the analogy of FIG. 3, the threetypes of flows described in connection with FIG. 3 are also shown inFIG. 4. The block 4 is received and stored in a first register 10 a. Atsubstantially the same time, the argument is received and stored in asecond register 10 b and the first program counter 7 a is received andstored in a third register 10 c. At the beginning of a clock tick, alogic unit 11 receives the block 4 and the argument 6 from the first andthe second register respectively. The first program counter 7 a is usedfor looking up a corresponding instruction stored in an editable, firstinstruction table 12 a, which is comprised in a storage means includedin the processing means 3. The first instruction table 12 a comprises atleast a first instruction 13 a, but here the first instruction table 12a also is illustrated with a second and third instruction, 13 b and 13 crespectively. Of course the first instruction table 12 a may comprise anarbitrary number of instructions. Each one of the instructions 13 a–ccomprises editable instruction fields (not shown). When an instructioncorresponding to the first program counter 7 a is found, the instructionis sent to the logic unit 11 for execution of operations correspondingto the instruction. In FIG. 4, the first instruction 13 a corresponds tothe first program counter 7 a. Therefore, the first instruction 13 a issent to the logic unit 11 for execution of the operations correspondingto the first instruction 13 a. An instruction field may for examplecomprise a jump condition instruction.

The logic unit 11 comprises means, i.e. a logic sub-unit, for creatingnew program counters and means for executing the operations associatedto a received instruction. In the first stage in this example, the meansfor executing the operations and compute conditional jumps is an ALU(Arithmetic Logic Unit). An ALU is known to a person skilled in the artand is therefore not described more in detail. Examples of additional oralternative means for executing the operations are means for picking outa part or parts of the block, means for inserting data in a block, suchas adding a new header to a packet, and a FPU (Floating Point Unit) forthe handling of floating point operations. After the first instruction13 a has been received by the logic unit 11, the operations necessaryfor carrying out the first instruction 13 a are executed. By way ofexample, the TOS (Type of Service) field in an IP-packet may bemodified. The logic unit 11 is also able to edit the argument 6.Moreover, based on the block 4, the argument 6, the operations performedon the block 4 and/or the argument 6 and/or desired conditional jumps,the logic unit 11 creates a second program counter 7 b. Before the clocktick, and thereby the first stage 9 a, has ended, the changed orunchanged block 4 is stored in a fourth register 10 d, the changed orunchanged argument 6 is stored in a fifth register 10 e and the secondprogram counter is stored in a sixth register 10 f.

The second stage 9 b during a subsequent clock tick works in a similarway as the first stage 9 a. Here, a second logic unit 14 receives themodified or unmodified block 4 and argument 6 from the fourth and fifthregister respectively. The second program counter 7 b is compared withinstructions in an editable, second instruction table 12 b, which inFIG. 4 comprises three instructions: a fourth instruction 13 d, a fifthinstruction 13 e and a sixth instruction 13 f. Of course theinstructions 13 d–13 f may be similar or identical to the instructions13 a–13 c in the first instruction table 12 a. In FIG. 4, the sixthinstruction 13 f corresponds to the second program counter 7 b. Thus,the second logic unit 15 receives the sixth instruction 13 f andexecutes the operations corresponding to the sixth instruction 13 f onthe received block 4 and/or argument 6 and sends the block 4 to aseventh register 10 g and the argument 6 to an eighth register 10 h. Thesecond logic unit 14 also creates a third program counter 7 c, which issent and stored in a ninth register 10 i.

As is indicated by FIG. 4, a new program counter is created in every newprocessing stage in the processing means 3. If a second module isserially coupled to the first module, a last argument of a firstprocessing means is stored in a register and constitutes a search vectorfor a second classification means comprised in the second module. FIG. 4also indicates the fact that editable instruction tables and differentlogic units, both in respect of physically different logic units and inrespect of entirely or partly different types of components comprised ineach logic unit, may be used for each one of the stages in theprocessing means 3. Altematively, instead of using different logic unitsfor each stage, some or all of the stages may share the same logic unit.Also enclosed by the invention is the use of only one editableinstruction table for some or every stage in the processing means.However, such an embodiment may limit the processing speed. It must alsobe stated that an instruction may only instruct the execution of anoperation that does affect neither the block 4, nor the argument 6. Suchan instruction could be used, for example, when a block only has beenidentified as one that only has to be transported through a stage, somestages or the whole processing means.

It shall be appreciated that the storage means comprising the editableinstruction tables used by the processing means 3, may be comprised inthe processing means 3 or outside of the processing means 3, but on themodule 1, or integrated in an IC (Integrated Circuit) 15, which alsocomprises at least one module 1. A circuit board assembly 16 isschematically illustrated in FIG. 5. Here the circuit board assembly 16comprises a local CPU 17, the IC 15 and a first and second interfacedevice, 18 a and 18 b respectively. An example of an application forsuch a circuit board assembly is in computer units for firewallappliances. The IC 15 comprises the serially coupled first module 1 anda second module 19. As is illustrated by a double-headed arrow 20, theIC 15 is able to communicate with the local CPU 17 via a bus. A moredetailed example of a communication between the IC 15 and the local CPU17 is described later in connection to FIG. 7. Throughout thedescription, the local CPU 17 is of a type known to a person skilled inthe art and is therefore not described more. An arrow 21 illustratesblocks coming in to the IC 15 from the first interface device 18 a. Theincoming blocks are processed by the serially coupled first and secondmodule, 1 and 19, and then sent back to the first interface device 18 a.Although not shown, blocks from the second interface device 18 b may ofcourse be processed in a similar way.

An example of a computer unit 22 that comprises modules according to theinvention will now be described. This example relates to a router, i.e.a computer that forwards packets from one LAN (Local Area Network) orWAN (Wide Area Network) to another. FIG. 6 schematically illustratesparts of a structure in the router, where several line cards, i.e.circuit board assemblies, each provided with a transmitting/receivingpart for a particular protocol, are arranged. Here only three line cards23 a–23 c are shown, but it may of course be more or less of them in therouter. Each line card comprises at least one IC 15, which comprises atleast one module 1 according to the invention. As also shown in FIG. 5,the local CPU 17 associated with every IC 15 may be positioned on eachline card 23 a–23 c. For applications demanding fast processing of a lotof data, optical fibres are used for connecting the line cards 23 a–23 cto a communications network (not shown). Each line card 23 a–23 ctherefore comprises a first set of ports, i.e. there are three sets ofthe first set of ports, which in FIG. 6 only are symbolised by the threelines 24 a–24 c with two arrowheads to the left of the line cards 23a–23 c. The line cards communicate with each other through a switchfabric card 25, i.e. a card comprising the architecture used by therouter for redirecting data coming in on one of the ports of the cardout to another of its ports. Thus the switch fabric card 25 serves as aswitch and junction for the line cards 23 a–23 c. Each line card 23 a–23c comprises a second set of ports, i.e. there are three sets of thesecond set of ports in FIG. 6, for the communication with the switchfabric card. Each second set of ports is symbolised by lines 26 a–26 cwith two arrowheads between the associated line card 23 a–23 c and theswitch fabric card 25. A device 27 is for example used for computingrouting tables, i.e. database tables in the router that containinformation of a current communications network. Through the device 27,a provider of the IC 15 may update the instructions in the editableinstruction tables 12 a–12 b disclosed above. However, the updating isnot a part of this invention and therefore not described more in detail.

FIG. 7 schematically shows an example of a circuit architecture on oneof the line cards 23 a–23 c, which includes a plurality of modulesaccording to the invention. Here, the first set of ports is connected toa multiplexor 28. A plurality of modules are serially coupled to themultiplexor 28 and lead to a unit 29 for operations such as queuing,scheduling and shaping. These operations are known to a person skilledin the art and are not a part of this invention. Additional modulesfollow after the unit 29, before the pipelined packets are delivered toan inverse multiplexor 30 and out via the second set of ports, whichcorrespond to the first set of ports. A feed-back to the multiplexor 28may also be done. Furthermore, the packets may be forwarded from theinverse multiplexor 30 to the local CPU 17 for processing. Also, the CPU17 may send packets to the multiplexor 28.

Examples of tasks, which may be performed in one of the modules in FIG.7, are:

decoding different types of packets, such as ATM-cells and Ethernetpackets;

firewalling for determining if a packet shall be forwarded to asubsequent module or filtered out;

firewalling in order to only forward certain types of packets from theline card;

traffic conditioning, i.e. measuring the length of the incoming packetand having a condition that may be that only a certain amount of data isallowed to be forwarded to a certain address in the communicationsnetwork and where all data above a limit is thrown away;

forwarding the packet to another line card using the routing table;

queue priority identification, for instance in the case where differentpackets have

different priorities regarding fast transmission through thecommunications network; and

adding or removing a header to or from an incoming packet.

The processing means 3, the method for the processing means 3 and themodule 1 described above is of course applicable to all kinds ofcomputer units, other than the router and computer units for firewallappliances described above, where the computer units would benefit frompipelining. Examples of such computer units are network computer unitssuch as: switches; gateways, i.e. computer units that perform protocolconversion between different types of networks and applications; andload balancing units for Web-servers.

The invention is also applicable for computer units involved in digitalsignal processing, i.e. the analysing and/or modifying of signals fromsources such as sound, weather satellites and earthquake monitors. Theblock 4 of data received by a module 1 may in this case be a digitalrepresentation of an analogue signal sequence. Fields where digitalsignal processing in connection with the invention is used, are e.g.biomedicine, sonar, radar, seismology, speech and music processing,imaging and communications.

1. A method for pipelined processing, comprising a plurality ofpipelined processing stages and wherein the method comprising the stepsof: receiving a block (4) in a first logic unit (11) in a processingmeans (3); looking up a first instruction (13 a) corresponding to afirst program counter (7 a), associated with the block (4) in a firstinstruction table (12 a) comprising at least the first instruction (13a); executing at least one operation associated with the firstinstruction (13 a) in the first logic unit (11); creating in the firstlogic unit (11) a second program counter (7 b), associated with theblock (4); receiving the block (4) in a second logic unit (14) in theprocessing means (3); looking up a further instruction (13 f)corresponding to the second program counter (7 b) in a secondinstruction table (12 b) comprising at least the further instruction (13f); and executing at least one operation associated with the furtherinstruction (13 f) in the second logic unit (14).
 2. A method accordingto claim 1, wherein the at least one pipelined processing stagecomprises the step of: receiving at least one argument (6) in the firstlogic unit (11), where the at least one argument (6) is associated withthe block (4); and the executing of the at least one operation in thefirst logic unit (11) is performed on the at least one argument (6), theblock (4) or both the at least one argument (6) and the block (4).
 3. Amethod according to claim 2, comprising the steps of: receiving a searchvector (5) associated with the block (4) in a classification means (2);comparing the search vector (5) with data stored in an associativestorage (8), the data comprising the first program counter (7 a) and theat least one argument (6); and sending the at least one argument (6) andthe first program counter (7 a) to the processing means (3) before anyof the stages of the plurality of pipelined processing stages.
 4. Amethod according to claim 1, comprising the steps of: creating a secondprogram counter (7 b) in a first stage (9 a), and creating a thirdprogram counter (7 c) in a second stage (9 b).
 5. A processing means (3)for processing pipelined data, comprising or connected to a storagemeans and comprising a plurality of logic units (11, 14) for executingoperations on a block (4) of data, wherein the storage means comprises aplurality of instruction tables (12 a, 12 b), each comprising at leastone instruction, and wherein a first logic unit (11) is connected to afirst register (10 a) for storing a block of data, a register forstoring a first program counter is connected to a first instructiontable (12 a), the first instruction table is connected to the firstlogic unit (11), the first logic unit (11) is connected to a furtherregister (10 d) for storing the block of data, and to a further register(10 f) for storing a second program counter, a second logic unit (14) isconnected to the further register (10 d) for storing the block of data,the further register (10 f) for storing a second program counter isconnected to a second instruction table, and the second instructiontable (12 b) is connected to the second logic unit (14).
 6. A processingmeans (3) according to claim 5, wherein the first logic unit isconnected to a register for storing at least one argument associatedwith the block of data.
 7. A processing means (3) according to claim 5,wherein at least one of the instruction tables (12 a) also comprises atleast a second instruction (13 b).
 8. A processing means (3) accordingto claim 5, wherein the block (4) is a PDU, e.g. a part of an IP-packet.9. A processing means (3) according to claim 5, wherein the block (4)comprises a digital representation of an analogue signal sequence.
 10. Aprocessing means (3) according to claim 5, wherein at least one of thelogic units (11) comprises an ALU.
 11. A processing means (3) accordingto claim 10, wherein the first logic unit (11) comprises means forpicking out a part or parts of the block (4).
 12. A module (1) forprocessing pipelined data, comprising a classification means (2) formatching or identifying a block (4) of data and a processing means (3)for processing the block (4), the processing means (3) connected tostorage means and comprising at least two logic units (11) for executingoperations on the block (4), which is delivered from the classificationmeans (2) to the processing means (3), wherein the processing meanscomprises a first register for storing a program counter, theclassification means being connected to the first register for storing aprogram counter, the storage means comprises a first instruction table(12 a) comprising at least one instruction, a first logic unit (11) isconnected to a first register (10 a) for storing the block, the firstregister for storing a first program counter is connected to the firstinstruction table, the first instruction table is connected to the firstlogic unit, the first logic unit is connected to a further register (10d) for storing the block of data, and to a further register (10 f) forstoring a second program counter, a second logic unit (14) is connectedto the further register (10 d) for storing the block of data, thefurther register (10 f) for storing a second program counter isconnected to a second instruction table (12 b), wherein the secondinstruction table is connected to the second logic unit (14).
 13. Amodule (1) according to claim 12, wherein the processing means comprisesa register for storing at least one argument, the classification meansbeing connected to the register for storing at least one argument, andthe at least one logic unit (11) in the at least one pipelinedprocessing stage is connected to a register for storing the at least oneargument.
 14. An integrated circuit (15), characterised by at least onemodule (1) according to claim
 12. 15. A circuit board assembly (16),such as a line card (23 a) adapted for a router, having at least oneintegrated circuit (15) comprising at least one module (1) forprocessing pipelined data, wherein said module comprising aclassification means (2) for matching or identifying a block (4) of dataand a processing means (3) for processing the block (4), the processingmeans (3) being connected to storage means and comprising at least twologic units (11) for executing operations on the block (4), which isdelivered from the classification means (2) to the processing means (3),and wherein the processing means comprises a first register (10 c) forstoring a program counter, the classification means being connected tothe first register for storing a program counter, wherein the storagemeans comprises a first instruction table (12 a) comprising at least oneinstruction, a first logic unit (11) is connected to a first register(10 a) for storing the block, the first register for storing a firstprogram counter is connected to the first instruction table (12 a), thefirst instruction table (12 a) is connected to the first logic unit(11), the first logic unit is connected to a further register (10 d) forstoring the block of data, and to a further register (10 f) for storinga second program counter, and a second logic unit (14) is connected tothe further register (10 d) for storing the block of data, the furtherregister (10 f) for storing a second program counter is connected to asecond instruction table (12 b), wherein the second instruction table isconnected to the second logic unit (14).
 16. A computer unit (22), suchas network computer unit or a signal processing computer unit,comprising at least one integrated circuit (15), wherein the at leastone integrated circuit (15) comprises at least one module (1) accordingto claim
 12. 17. A pipelined processing system, comprising aclassification means (2) for matching or identifying a block (4) ofdata, a storage means and a processing means (3) for processing theblock (4), the processing means (3) being connected to storage means andcomprising at least two logic units (11) for executing operations on theblock (4), which is delivered from the classification means (2) to theprocessing means (3), wherein, the processing means comprises a firstregister for storing a program counter, the classification means beingconnected to the first register for storing a program counter, thestorage means comprises a first instruction table (12 a) comprising atleast one instruction, a first logic unit (11) is connected to a firstregister for storing the block, the first register for storing a firstprogram counter is connected to the first instruction table (12 a), thefirst instruction table (12 a) is connected to the first logic unit(11), the first logic unit is connected to a further register (10 d) forstoring the block of data, and to a further register (10 f) for storinga second program counter, a second logic unit (14) is connected to thefurther register (10 d) for storing the block of data, the furtherregister (10 f) for storing a second program counter is connected to asecond instruction table (12 b), and the second instruction table (12 b)is connected to the second logic unit (14).
 18. A pipelined processingsystem according to claim 17, wherein the processing means comprises aregister for storing at least one argument, the classification meansbeing connected to the register for storing at least one argument, andthe at least one logic unit (11) in the at least one processing stage isconnected to a register for storing the at least one argument.